1. Technical Field
The present disclosure relates to the driving configuration of a switch and, more specifically, to a driving configuration of a switch realized by means of a first and a second transistor connected in series to each other and to the relative intrinsic diodes in antiseries and driven by a driving device, including, without limitation, a driving configuration of a high voltage (HV) switch.
2. Description of the Related Art
As is well known, a driving device of a high voltage (HV) switch, usually realized by means of a MOS transistor, is specified to instantaneously follow the voltage dynamics of a signal to be switched.
In general, a switch realized by means of a high voltage MOS or DMOS transistor is able to manage high voltages between its drain and source terminals, as well as with respect to a substrate potential. The highest voltage value Vgs between its gate and source terminals is however limited to some volts (3V or 5V).
In particular, when the switch is off it must be able to interrupt the passage of current independently from the voltage polarity at its ends. Further to the connection of the body terminal to the source terminal, a junction is created between the source and drain terminals, which prevents the inversion of the polarity across the switch without triggering a passage of current in the intrinsic diode thus created even if the relative channel is off.
To overcome this drawback, the switch is realized by placing two MOS or DMOS transistors in series, so that the relative intrinsic diodes are biased in antiseries, i.e., with a pair of corresponding terminals, in particular respective anodes, in common. In this way, at least one intrinsic diode of the switch is always inversely biased.
In this case a driving device or driver is to be provided that is able to follow a turn on/off command of the switch and to apply a first turn on voltage value (for example equal to 5V) between the gate and source terminals of the transistors contained in the switch when the switch itself is to be turned on and a second turn off voltage value (for example equal to 0V) between the gate and source terminals of the transistors contained in the switch when it is to be turned off.
Schematically shown in FIG. 1 is a configuration 5 of a driven switch including a switch 1 realized by means of two DMOS transistors, DM1, DM2, connected in series with intrinsic diodes in antiseries and driven by means of a driving device or driver 2.
In particular, this configuration 5 has a resistive element Rgs that connects respective common source SS and gate GG terminals of the DM1 and DM2 transistors of the switch 1. The DM1 and DM2 transistors also have respective drain terminals, D1 and D2.
The driver 2 is inserted between a first and a second voltage reference, respectively a supply Vss (for example equal to 3.3V) and a ground GND (for example equal to 0V), and it has an input terminal IN receiving a driving signal Sin for driving the switch 1 in a first on state (ON) and in a second off state (OFF). In particular, the driving signal Sin is a digital signal having a first level or 0 logic corresponding to a demand for turn on of the switch 1 and a second level or 1 logic corresponding to a demand for turn off of the switch 1.
The driver 2 also has an output terminal, OUT, connected, by means of a level shifter 3 to the gate terminals GG of the switch 1. On the output terminal OUT of the driver 2 there is a control signal Sc for the switch 1, derived from the driving signal Sin applied to its input terminal IN
In fact, it is to be emphasized that in high voltage applications the voltage value at the drain and source terminals of the transistors in the switch 1 must take all the values between a negative −HV and a positive +HV high voltage reference, for example equal to 100V and a level shifter 3 is thus to be used. The shifter is able to shift a control signal Sc referred to the ground GND and to refer it to an instantaneous level of a signal Scomm to be switched and applied to a terminal of the switch 1, in particular to the D1 and D2 drain terminals.
As shown in FIG. 1, the level shifter 3 is realized in a simple and functional way so as to convert the control signal Sc in voltage (referred to the GND) into a control signal in current and then again into a control signal Scd derived in voltage referred to the common source terminals SS of the DM1 and DM2 transistors comprised in the switch 1.
For realizing this conversion, the level shifter 3 includes a first transistor M1 having a control or gate terminal connected to the output terminal OUT of the driver 2, a first conduction terminal, in particular a source terminal, connected, by means of the parallel of a current generator CSG (in particular a low voltage one) and of a capacitor Cff (so called feed forward capacitor), to the GND, as well as a second conduction terminal, in particular a drain terminal, connected to a shifted voltage reference VPP (equal to a high voltage value, for example +3V) by means of a current mirror realized by a second M2 and a third M3 transistor.
In particular, the second transistor M2 is inserted between the shifted voltage reference VPP and the drain terminal of the first transistor M1, it is diode configured, and it has a gate terminal connected to the gate terminal of the third transistor M3, in turn inserted between the shifted voltage reference VPP and an output terminal OUT* of the level shifter 3, in turn connected to the gate terminals GG of the switch 1.
Although advantageous under several aspects, this known configuration shows a serious drawback linked to the sizing of the resistive element Rgs inserted between the common gate GG and the source SS terminals of the DM1 and DM2 transistors of the switch 1.
In fact, if the switch 1 is to be switched quickly, this resistive element Rgs is to be sized with a relatively small value so that the time constant T given by the resistive element Rgs itself and by the parasitic capacitances Cpar associated with the gate nodes is brief and smaller than a switch time Tcomm (in this case, a turn off time) desired. In particular, it results in:T=Rgs*Cpar<Tcomm  (1)
Thus, by using a small resistance value for the resistive element Rgs so as to meet the above reported relation (1), a high current value Ion is however to be provided during the turn on, this current value having in fact to meet, for the voltage between the gate and source terminals of the DM1 and DM2 transistors, the following relation:Vgs=Rgs*Ion=5V  (2)
In other words, the configuration 5 shown in FIG. 1 must use a variable resistance being small when the switch 1 is off and high when it is on.
Such a configuration 5, using a resistive element Rgs of 500 kOhm, has been simulated in which the switch 1 connects a load to a source of a voltage signal Vs. The results of this simulation are shown in FIGS. 2A, 2B, and 2C. In particular, FIG. 2A shows a control signal Sc of the switch 1, for which a void voltage value (Sc=0) corresponds to a condition of open switch, and a voltage value equal to Vpp (Sc=5V) corresponds to a condition of closed switch. FIG. 2B shows the supply voltage signal Vpp, the source voltage signal Vs, and the voltage signal that is obtained on the load Vload, overlapped onto each other, while FIG. 2C reports the signal on the load Vload only. Thus, the switch 1 works correctly and reports the source voltage value Vs on the load (Vload signal overlapped onto Vs in FIG. 2B) as soon as the control signal Sc is brought to Vpp (turn on of the switch 1). This switch 1 does not however work correctly during the turn off (Sc is brought back to 0) since the voltage signal on the load Vload dampens only gradually starting from 20 microseconds (time in which the control signal Sc is interrupted in FIG. 2C), the turn off being relied only upon the resistive element Rgs. From these results, it is immediate to verify how such a value of the resistive element Rgs thus implies a long turn off time of the switch 1.
The technical problem is that of providing a driving configuration of a high voltage switch able to associate, with a quick switch transient, a reasonable control current value while overcoming the limits and drawbacks still affecting the configurations realized according to the foregoing description.